Documentation
make
Documentation table of contents.
Introduction
The make utility maintains, updates, and regenerates programs and files. make is primarily used for compiling programs that contain multiple files, and is available on UBUnix.
Setup
Ensure that the default system search path is included in your search path,
and that your MANPATH environment variable includes the default value for
it. You can set the $MAKEFLAGS environment
variable to specify commonly used flags. To set $MAKEFLAGS
to the -d and -s
flags, enter:
setenv MAKEFLAGS ds
Using make
The make command can be executed by entering:
make
make looks in the current directory
at a file named Makefile for instructions.
The instructions for make are targets, dependencies, and rules. Rules are
shell commands. The format of a target entry in a makefile is as follows:
target: dependency list
rule
rule
...
target is the file you would like
to have created by the specified (target) entry. The dependency
list is a list of filenames that must exist before any rules can
be executed. rule is a shell command
and must be preceded by a Tab. (The rule
updates the target file.) Executing the rule successfully is called building
the target. make only builds a target if the target has an older modification
time than any file in the dependency list. Below is an example of a makefile:
# This is a comment line.
# This makefile compiles the modula2
# program named "prog.mod".
prog1: prog.mod
M2c -o prog1 -e prog prog.mod
The target is prog1, the dependency list is prog.mod, and the rule is m2c -o prog1 -e prog prog.mod. make looks to see if prog.mod exists, and has been modified more recently than prog1. If this is true, then make executes the rule m2c -o prog1 -e prog prog.mod. This rule compiles the program named prog.mod and names the executable prog1, thus building the target.
Flags
The following are command line arguments for make:
| Flag | Description |
|---|---|
| -d | Displays reasons for rebuilding a target. |
| -dd | Displays dependency checks and processing in detail. |
| -D | Lists the contents of the makefile used. |
| -e | Uses environment variables instead of % of variables assigned in the makefile that possesses the same name. |
| -f makefile | Uses the named makefile. Makefile is the default. |
| -i | Ignores error codes returned by rules. |
| -k | Abandons work on the current target if a rule is unsuccessful, but continues with other targets that do not depend upon the current target. |
| -n | Lists rules but does not execute them. |
| -p | Prints macro definitions and target descriptions. |
| -s | Does not print rules when they are executed. |
| -S | Exits when a target is unsuccessfully updated. |
| -t | Sets modification times of all target files to current. |
Multiple targets
It is possible to have multiple targets in a single makefile. Each line
that does not begin with a Tab or
# begins a new target entry:
target entry
target entry
If a file in the dependency list is a target, make builds the dependency
first. For example:
game: test.o player.o
acc test.o player.o -o game
test.o: test.c
acc -c test.c
player.o: player.c
acc -c player.c
In summary of what is happening here:
- The targets are game, test.o, and player.o. make tries to build game, but it sees that test.o and player.o are also targets.
- make tries to build the test.o and player.o target entries. To build test.o, the file test.c must exist. If it does, make executes the rule acc -c test.c, which creates a file named test.o.
- Now make tries to build player.o. If player.c exists, then it executes the rule acc -c player.c, which creates the file player.o.
- Now that player.o and test.o exist, the rule for the target game can be executed. The game rule acc test.o player.o -o game creates the final target file named game.
make only builds a target if a dependency has been modified after the target was modified. If you change the file named player.c, and execute make, only player.o and game are built. It does not build test.o, because test.o was changed after test.c; thus, an update is not necessary.
If you have multiple targets that are independent of each other (not related
by dependencies), you can have them built by using a target named all
and having the targets in the dependency list:
all: server client
server: server.c
acc server.c -o server
client: client.c
acc client.c -o client
clean:
rm *.o server client
In this example, targets server
and client are built. The target
clean removes all .o
files and the files named server
and client only if the clean
target is specified on the command line:
make clean
To build the clean target each time make is executed, clean would have to be included in the target all.
Macros
A macro can be defined in a makefile.
You can place it in the makefile
or specify it on the command line:
variable=value
If you define a one character variable, you must precede it with a dollar-sign
($) when referring to it. If the
variable is more that one character long, it must be surrounded by parentheses
and then preceded by a dollar-sign ($).
The following makefile defines F
to have the value -g, and CC
to have the value acc:
CC = acc
F = -g
prog1: prog.c
$(CC) $F prog.c -o prog1
The above makefile is identical to:
prog1: prog.c
acc -g prog.c -o prog1
The value of a macro can be changed on the command line:
make variable=value
The variable specified on the command line takes precedence over the one
specified in the makefile. In the
makefile above, to change the value
of CC from acc
to gcc, use the following command
line:
make CC=gcc
Additional Information
For more complete information on make, read the online manual page by
entering:
man make